Because, in particular, of the ever decreasing supply voltage in integrated circuits, random dopant fluctuations (RDFs), deterioration and aging over time, carrier mobility fluctuations, gate oxide thickness fluctuations and channel width fluctuations, it is preferable to employ various read and write assist mechanisms or techniques, in particular the write assist mechanisms that make provision to decrease the positive supply voltage Vdd, to increase the negative supply voltage Vss, to boost word lines and to boost negative bit lines, in order to ensure robust writability to these SRAM cell circuits.
However, these write assist mechanisms are generally permanently applied on a large scale, for example to all of the SRAM cell circuits of a static random access memory, thereby permanently increasing, in particular, the consumption or dynamic power of said static random access memory.
Furthermore, SRAM cell circuits are much more sensitive to the decrease in positive supply voltage Vdd than other standard logic gates, since this voltage Vdd is critical to the correct operation of each transistor in a SRAM cell circuit.
Consequently, it may be detrimental to decrease the supply voltages Vdd for SRAM cell circuits for the purpose of decreasing their dynamic power (consumption).